1. Field of the Invention
The present invention relates to a non-volatile memory and more specifically to a reprogrammable memory point.
2. Discussion of the Related Art
FIGS. 1 and 2, respectively, are a top view and a cross-section view of a non-volatile memory point. This memory point is described in International patent application WO 03/088366 which is incorporated herein by reference. This memory point is formed in and above a semiconductor substrate 1, for example, made of lightly-doped P-type silicon. Two N-type doped wells 2 and 3 are respectively formed to the left and to the right of FIG. 2. A floating gate 5, for example, made of polysilicon, is placed on substrate 1. Floating gate 5 comprises a substantially ring-shaped portion 6 placed above well 2 and which extends in a rectilinear portion 7, having its end placed above well 3. Floating gate 5 is insulated from the substrate by a thin insulating layer 8, for example, silicon oxide. A heavily-doped P-type area 10 is placed at the surface of N well 2 inside of ring-shaped portion 6 in top view. A heavily-doped P-type area 11 is placed at the surface of N well 2 all around ring-shaped portion 6 in top view. A heavily-doped N-type well contact area 15 is placed at the surface of N well 2. Similarly, a heavily-doped N-type well contact area 16 is formed at the surface of N well 3 to the right thereof. A heavily-doped P-type area 17 is formed at the surface of N well 3 to the left of N+ region 16 and all around, in top view, rectilinear portion 7 of floating gate 5. N wells 2 and 3 are surrounded with an insulating area formed in the upper portion of substrate 1. Three portions 20, 21, and 22 of this insulating area are visible respectively to the left of well 2, between wells 2 and 3, and to the right of well 3. Further, N+ area 15 and P+ area 11 are separated by an insulating area 23 formed in the upper portion of N well 2. Heavily-doped areas 10, 11, 15, 16, and 17, as well as floating gate 5 are covered with silicide layers, not shown.
FIG. 3 is an equivalent electric diagram of the memory point of FIGS. 1 and 2. Ring-shaped portion 6 of floating gate 5 forms the gate of a P-channel K transistor (PMOS) T1. P+ areas 10 and 11 respectively form a drain area D and a source area S. N well 2 forms “bulk” B of transistor T1. The end of rectilinear portion 7 of floating gate 5 forms the gate of a PMOS transistor T2. P+ area 17 is both the source area and the drain area of transistor T2. The source and drain areas are short-circuited and connected to the substrate of transistor T2, which is formed by N well 3, via the silicide layer covering P+ and N+ areas 16 and 17. N well 3 and P+ and N+ areas 16 and 17 form a control electrode C of the memory point. The gates of PMOS transistors T1 and T2 are connected via floating gate portion 7. References B, D, S, and C have been written again in FIG. 2 for clarity.
The memory point programming or erasing respectively comprises the injection of electric charges into floating gate 5 or the elimination thereof. Methods for programming, erasing, or reading from such a memory point are described in detail in the above-mentioned International patent application.
A well-known problem of non-volatile memory points is the “leakage” of the charges stored in the floating gate. In the previously-described memory point example, the charges stored in floating gate 5 tend to pass, by tunnel effect, through insulating layer 8 towards the semiconductor regions of transistors T1 and T2. Such tunnel-effect charge leakages become more significant as insulating layer 8 becomes thin. Further, the multiple operations of programming and erasing of such memory points result in deteriorating the quality of thin insulating layer 8 and in further increasing tunnel-effect leakages.